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IEICE A Complete Library of Cross-Bar Gate Logic with Three Control Inputs

Ryosuke Matsuo , Shin-ichi Minato

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2023

査読有り筆頭著者
IEICE A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits

Ryosuke Matsuo , Jun Shiomi , Tohru Ishihara , Hidetoshi Onodera , Akihiko Shinya , Masaya Notomi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. 104-A, no. 11, pp. 1546–1554, 2021

査読有り筆頭著者
IEICE Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits

Ryosuke Matsuo , Jun Shiomi , Tohru Ishihara , Hidetoshi Onodera , Akihiko Shinya , Masaya Notomi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. 102-A, no. 12, pp. 1751–1759, 2019

査読有り筆頭著者

国際会議プロシーディング

DAC A Correlation-Aware GKP Decoder for Fault-Tolerant Continuous-Variable Photonic Quantum Computers

Ryosuke Matsuo , Junichiro Kadomoto

Design Automation Conference (DAC), 2026

査読有り筆頭著者
IEEE QCE Towards a Measurement-Based Quantum Computing Architecture Using Continuous-Variable Optical Qubits

Ryosuke Matsuo , Junichiro Kadomoto

IEEE International Conference on Quantum Computing and Engineering (QCE), 2025

査読有り筆頭著者
IEEE QCE On-chip optical pulse modulation for scalable superconducting quantum computers

Ryosuke Matsuo , Hidehisa Shiomi , Jun Shiomi

IEEE International Conference on Quantum Computing and Engineering (QCE), 2025

査読有り筆頭著者
TAU Ternary logic operation of CMOS inverters under low-temperature and low-voltage conditions

Kotaro Tominaga , Ryosuke Matsuo , Yoshihiro Midoh , Noriyuki Miura , Michihiro Shintani , Jun Shiomi

ACM/IEEE International Workshop on Timing Issues (TAU), pp. 36–42, 2025

査読有り
IEEE QCE Square-wave defined pulse generator for high fidelity gate operation of superconducting qubits

Ryosuke Matsuo , Kazuhisa Ogawa , Hidehisa Shiomi , Makoto Negoro , Ryutaro Ohira , Takefumi Miyoshi , Michihiro Shintani , Hiromitsu Awano , Takashi Sato , Jun Shiomi

IEEE International Conference on Quantum Computing and Engineering (QCE), pp. 378–379, 2024

査読有り筆頭著者
ASPDAC Optimizing Decision Diagrams for Measurements of Quantum Circuits

Ryosuke Matsuo , Rudy Raymond , Shigeru Yamashita , Shin-ichi Minato

Proceedings of the 29th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 134–139, 2024

査読有り筆頭著者
DATE Space and Power Reduction in BDD-based Optical Logic Circuits Exploiting Dual Ports

Ryosuke Matsuo , Shin-ichi Minato

Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1071–1076, 2022

査読有り筆頭著者
ISVLSI BDD Variable Ordering for Minimizing Power Consumption of Optical Logic Circuits

Ryosuke Matsuo , Shin-ichi Minato

IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 96–101, 2021

査読有り筆頭著者
ISVLSI A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing

Ryosuke Matsuo , Jun Shiomi , Tohru Ishihara , Hidetoshi Onodera , Akihiko Shinya , Masaya Notomi

IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 488–493, 2020

査読有り筆頭著者
ASPDAC BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing

Ryosuke Matsuo , Jun Shiomi , Tohru Ishihara , Hidetoshi Onodera , Akihiko Shinya , Masaya Notomi

Proceedings of the 24th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 203–209, 2019

査読有り筆頭著者

国内会議プロシーディング

IEICE-TR 完全準同型暗号TFHEにおける公開鍵サイズを考慮した多項式乗算アーキテクチャに関する検討

中川智文 , 松尾亮祐 , 池田誠

信学技報 (HWS2026-6), vol. 126, no. 4, pp. 29–34, 2026
QS研量子回路の観測のための決定グラフの最適化

松尾亮祐 , ルディー・レイモンド , 湊真一 , 山下茂

第9回量子ソフトウェア研究発表会, 2023

筆頭著者
DAシンポ 3入力関数に対するゲート数最小のクロスバーゲートロジック回路の列挙

松尾亮祐 , 湊真一

DAシンポジウム2022, pp. 227–233, 2022

筆頭著者
DAシンポ BDDに基づく光論理回路における双対端子を利用した面積と電力の削減手法

松尾亮祐 , 湊真一

DAシンポジウム2021, pp. 32–38, 2021

筆頭著者
ガイア BDDに基づく光論理回路の消費電力を最小化する変数順序付け

松尾亮祐 , 湊真一

デザインガイア2020, pp. 78–83, 2020

筆頭著者
DAシンポ二分決定グラフに基づく光論理回路の消費電力削減手法

松尾亮祐 , 塩見準 , 石原亨 , 小野寺秀俊 , 新家昭彦 , 納富雅也

DAシンポジウム2019, pp. 87–92, 2019

筆頭著者
IEICE-TR BDDに基づく光論理回路の素子数削減と消費電力低減

松尾亮祐 , 塩見準 , 石原亨 , 小野寺秀俊 , 新家昭彦 , 納富雅也

電子情報通信学会技術報告 (VLD2018), pp. 139–144, 2019

筆頭著者招待

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